On the Use of Ashenhurst Decomposition Chart as an Alternative to Algorithmic Techniques in the Synthesis of Multiplexer-Based Logic Circuits

Abstract

The non-uniqueness of a multiplexer implementation of a Boolean function results from the partition of the function variables into data select and data input variables. This partition affects critically the cost and structure of the final multiplexer realisation. Hence the central problem in the synthesis of logic circuits with multiplexers is the selection of that partition which results in the desired structure or the most economical realisation of the function. In this paper, the Ashenhurst decomposition chart is shown to be a mapping technique which solves this selection problem and enables the design of logic circuits with desirable attributes using multiplexers. The Ashenhurst decomposition chart also serves as a bridging technique between the map based and algorithmic based digital design methods in the synthesis of logic circuits with multiplexers.