Designing TCP/IP Checksum Function for Acceleration in FPGA

Abstract

Over the years network transmission speeds have improved greatly without a corresponding increase in the processing speed of the host processor. Traditionally, network protocol processing is handled in the CPU of the host computer. However, with devices featuring advanced connectivity and Internet functionality, protocol processing has created a heavy workload on the general processing processors, with additional constraints by the slower I/O bus speed limits. Consequently, for a higher throughput and speedy delivery of information between hosts on the internet, there is the need to identify those performance-critical TCP/IP functions and accelerate them in order to match the transmission speeds with the protocol processing speeds. Based on profiling results, a micro-level function, namely checksum is observed to be a computational intensive function. In this paper, the checksum function is selected and implemented in an FPGA. The checksum calculation is implemented based on 16-bit one’s complement adders. In all, by minimizing the functional overhead, such as, instruction fetching and decoding, bus speed constraints, latency due to buffer/memory transfer; and providing flexibility by configuration possibilities, the high speed and cost advantage are made possible.