Performance Evaluation of Hyper Threading Technology Architecture Using Microsoft Operating System Platform

  • O.E. Okonta
  • D. Ajani
  • A.A. Owolabi
  • E.E. Imiere
  • L. Uzomah
Keywords: Hyper-Threading, core circles, code efficiency, processor resource utitilization, applications performance.


This paper describes the Hyper-Threading Technology architecture, and discusses the micro architecture details of Intel's structure. Hyper-Threading Technology is an important addition to Intel’s enterprise product line and has been integrated into a wide variety of products. Intel provides Hyper-Threading (HT) in processors based on its Pentium and more recent processor die. HT enables two threads to execute on each core in order to hide latencies related to data access. These two threads can execute simultaneously, filling unused stages in the functional unit pipelines. To aid better understanding of HT related issues, we look at Performance Monitoring Unit (PMU) data (instructions retired; un-halted core cycles; L2 and L3 cache hits and misses; vector and scalar floating-point operations, etc.). We then use the PM data to make deduction on a new metric of efficiency in order to quantify processor resource utilization and make comparisons of that utilization between single-threading (ST) and HT modes. We also study performance gain using unhalted core cycles, code efficiency of using vector units of the processor, and the impact of HT mode on various shared resources like L2 and L3 cache. Results using four full-scale, productionquality scientific applications from computational fluid dynamics indicate that HT generally improves processor resource utilization efficiency, but does not necessarily translate into overall application performance gain.

Key words: Hyper-Threading, core circles, code efficiency, processor resource utitilization, applications performance.


Journal Identifiers

print ISSN: 1116-5405