Comparison of D-Latch based on CNTFET & DLatch based on MOSFET using HSPICE

Abstract

D-Latch has applications in Memory cells and Low power D-Latchs are important for low-power digital designs. In this paper, presents design of the low power & high speed D-Latch using carbon nanotube field effect transistor (CNTFET) that utilizes different threshold voltages for best performance. In this paper, proposed design of D-Latch is simulated with HSPICE models, cmos 32nm ptm and CNTFET 32nm which Presented by Stanford University. MOSFET and CNTFET designs are simulated in different voltage & 1MHz up to 1GHz frequency and their performances are compared. The simulation result shows that the proposed D-Latch design based on CNTFET achieved an improvement in the output parameters. Finally the results of power, Delay and power delay product show that this design based on CNTFET is more optimal than its  MOSFET design.

Keywords: Low power D-Latch; CNTFET; Carbon nanotubes Field effect transistors;
power delay product (PDP)