Retracted: 4x4 bit Vedic multiplier using 13T hybrid full adder in 90 nm CMOS technology

  • S.J. Lee
  • S. H. Ruslan
Keywords: Vedic Mathematics, hyrbrid full adder, low power, multiplier.

Abstract

This article was withdrawn and retracted by the Journal of Fundamental and Applied Sciences and has been removed from AJOL at the request of the journal Editor in Chief and the organisers of the conference at which the articles were presented (www.iccmit.net). Please address any queries to editor@jfas.info.
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eISSN: 1112-9867